Thin film transistor substrate and method of manufacturing the same

ABSTRACT

A thin film transistor substrate with good process efficiency and a method of manufacturing the same are provided. The thin film transistor substrate includes a first conductive type MOS transistor and a second conductive type MOS transistor. The first conductive type MOS transistor includes a first semiconductor layer formed on a blocking layer and having first conductive type low-concentration doping regions adjacent to both sides of a channel region, first conductive type source/drain regions adjacent to the first conductive type low-concentration doping regions, a first gate insulating layer formed on the first semiconductor layer, a second gate insulating layer formed on the first gate insulating layer and overlapping with the channel region and the low-concentration doping regions of the first semiconductor layer, and a first gate electrode formed on the second gate insulating layer. The second conductive type MOS transistor includes a second semiconductor layer formed on the blocking layer and having second conductive type source/drain regions adjacent to both sides of a channel region, the first gate insulating layer formed on the second semiconductor layer, a third gate insulating layer formed on the first gate insulating layer and overlapping with the second semiconductor layer, and a second gate electrode formed on the third gate insulating layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional of U.S. patent application Ser. No. 11/502,806,filed on Aug. 11, 2006 now U.S. Pat. No. 7,682,881, which applicationclaims priority from Korean Patent Application No. 10-2005-0074582 filedon Aug. 13, 2005 in the Korean Intellectual Property Office, thedisclosures of which are incorporated herein by reference in theirentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin film transistor substrate and amethod of manufacturing the same. More particularly, the presentinvention relates to a thin film transistor substrate with good processefficiency and a method of manufacturing the same.

2. Description of the Related Art

Recently, in liquid crystal displays (LCDs) used as display devices fornotebook computers or other portable devices, driving methods thereofare shifting from a simple matrix type to an active matrix type. Inparticular, a thin-film transistor (TFT) active matrix driving method inwhich a plurality TFTs are formed on a glass substrate has become themainstream technology for driving the LCDs.

A TFT generally includes a gate electrode as a part of a gate line, asemiconductor layer forming a channel, a source electrode as apart of adata line, and a drain electrode opposite the source electrode about thesemiconductor layer. The TFT is generally used as a switching elementfor transmitting to or blocking from a pixel electrode a picture signalreceived through the data line by a scanning signal transferred throughthe gate line.

The semiconductor layer typically comprises amorphous silicon orpolycrystalline silicon. Thin-film transistors are categorized into abottom-gate type and a top-gate type according to the relative positionof the semiconductor layer to a gate electrode. A polycrystallinesilicon TFT is usually of a top gate type in which a gate electrode isformed above a semiconductor layer.

Along with the development of various crystallization techniques usinglasers, such a polycrystalline silicon TFT can be manufactured in atemperature range similar to that of an amorphous silicon TFT whilehaving higher electron or hole mobility than the amorphous silicon TFT,thereby realizing a Complementary Metal-Oxide Semiconductor (CMOS) TFTincluding an NMOS TFT with an n channel and a PMOS TFT with a p channel.Consequently, the polycrystalline silicon TFT can be utilized primarilyfor a driving circuit on a large-area glass substrate.

In conventional methods of manufacturing CMOS thin film transistors,however, the upper structures of semiconductor layers and ionimplantation regions in the semiconductor layers of NMOS and PMOStransistors are formed using separate photolithography processes, whichmakes a manufacturing process complicated and increases manufacturingcosts.

SUMMARY

The present invention provides a thin film transistor substrate withgood process efficiency.

The present invention also provides a method of manufacturing a thinfilm transistor substrate with good process efficiency.

According to an aspect of the present invention, there is provided athin film transistor substrate including a first conductive type MOStransistor and a second conductive type MOS transistor. The firstconductive type MOS transistor includes a first semiconductor layerformed on a blocking layer and having first conductive typelow-concentration doping regions adjacent to both sides of a channelregion, first conductive type source/drain regions adjacent to the firstconductive type low-concentration doping regions, a first gateinsulating layer formed on the first semiconductor layer, a second gateinsulating layer formed on the first gate insulating layer andoverlapping with the channel region and the low-concentration dopingregions of the first semiconductor layer, and a first gate electrodeformed on the second gate insulating layer. The second conductive typeMOS transistor includes a second semiconductor layer formed on theblocking layer and having second conductive type source/drain regionsadjacent to both sides of a channel region, the first gate insulatinglayer formed on the second semiconductor layer, a third gate insulatinglayer formed on the first gate insulating layer and overlapping with thesecond semiconductor layer, and a second gate electrode formed on thethird gate insulating layer.

According to another aspect of the present invention, there is provideda method of manufacturing a thin film transistor substrate, the methodincluding providing a substrate wherein first and second semiconductorlayers are formed on a blocking layer. Formed on the first semiconductorlayer are a first ion implantation mask structure comprising a firstgate insulating layer, a second gate insulating layer overlapping with achannel region and low-concentration doping regions of the firstsemiconductor layer, a first gate electrode overlapping with the channelregion of the first semiconductor layer, and a first photoresist filmpattern overlapping with the second gate insulating layer. Formed on thesecond semiconductor layer are a second ion implantation mask structurecomprising the first gate insulating layer, a third gate insulatinglayer overlapping with the second semiconductor layer, a second gateelectrode overlapping with a channel region of the second semiconductorlayer, and a second photoresist film pattern overlapping with the secondgate electrode, and forming second conductive type source/drain regionsby injecting a high-concentration second conductive type impurity ioninto the second semiconductor layer and into the blocking layer underthe first semiconductor layer using the first and second ionimplantation mask structures as ion implantation masks.

The scope of the invention is defined by the claims, which areincorporated into this section by reference. A more completeunderstanding of embodiments of the present invention will be affordedto those skilled in the art, as well as a realization of additionaladvantages thereof, by a consideration of the following detaileddescription of one or more embodiments. Reference will be made to theappended sheets of drawings that will first be described briefly.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing in detail exemplary embodimentsthereof with reference to the attached drawings in which:

FIG. 1 is a schematic diagram illustrating a thin film transistorsubstrate according to an embodiment of the present invention;

FIG. 2 is a sectional view of a driving unit of a thin film transistorsubstrate according to an embodiment of the present invention;

FIG. 3 is a flow diagram illustrating a method of manufacturing a thinfilm transistor substrate according to an embodiment of the presentinvention;

FIGS. 4 through 12 are sequential sectional views illustrating themethod of manufacturing the thin film transistor substrate according toan embodiment of the present invention;

FIG. 13 is a flow diagram illustrating a method of manufacturing a thinfilm transistor substrate according to another embodiment of the presentinvention; and

FIG. 14 is a sectional view of an intermediate structure formed in themethod of manufacturing the thin film transistor substrate according toanother embodiment of the present invention.

Embodiments of the present invention and their advantages are bestunderstood by referring to the detailed description that follows. Itshould be appreciated that like reference numerals are used to identifylike elements illustrated in one or more of the figures. It should alsobe appreciated that the figures may not be necessarily drawn to scale.

DETAILED DESCRIPTION

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. The samereference numbers indicate the same components throughout thespecification. In the attached figures, the thickness of layers andregions is exaggerated for clarity.

It is noted that the use of any and all examples, or exemplary termsprovided herein is intended merely to better illuminate the inventionand is not a limitation on the scope of the invention unless otherwisespecified. The use of the terms “a” and “an” and “the” and similarreferents in the context of describing the invention (especially in thecontext of the following claims) are to be construed to cover both thesingular and the plural, unless otherwise indicated herein or clearlycontradicted by context. The terms “comprising,” “having,” “including,”and “containing” are to be construed as open-ended terms (i.e., meaning“including, but not limited to,”) unless otherwise noted. It will beunderstood that when an element such as a layer, region or substrate isreferred to as being “on” another element, it can be directly on theother element or intervening elements may also be present. Furthermore,relative terms such as “beneath” may be used herein to describe arelationship of one layer or region to another layer or region relativeto a substrate or base layer as illustrated in the figures. In addition,the term “directly” means that there are no intervening elements. Asused herein, the term “overlapping” refers to the state that when one oftwo structures which are formed in different layers is disposed at thesame level as the other structure by a vertical access method, the areaof one structure is substantially included in the area of the otherstructure. It can also be applied to the case where another structure isinterposed between the two structures. Unless defined otherwise, alltechnical and scientific terms used herein have the same meaning ascommonly understood by one of ordinary skill in the art to which thisinvention belongs. Further, unless defined otherwise, all terms definedin generally used dictionaries may not be overly interpreted.

Hereinafter, a thin film transistor substrate according to an embodimentof the present invention and a method of fabricating the same will bedescribed in detail with reference to FIGS. 1 through 12.

FIG. 1 is a schematic diagram illustrating a thin film transistorsubstrate according to an embodiment of the present invention. Referringto FIG. 1, the thin film transistor substrate includes a pixel unit 10,a gate driver 20, and a data driver 30.

The pixel unit 10 includes a plurality of pixels connected to aplurality of gate lines G1, . . . , Gn and a plurality of data lines D1,. . . , Dm. Each pixel includes a switching device M connected tocorresponding gate and data lines, and a liquid crystal capacitor Clcand a storage capacitor Cst connected to the switching device M.

The plurality of the gate lines G1, . . . , Gn extending in a row (orhorizontal) direction are responsible for scan signal transmission tothe switching device M, and the plurality of the data lines D1, . . . ,Dm extending in a column (or vertical) direction are responsible forgray voltage (corresponding to an image signal) transmission to theswitching device M. The switching device M is a three-terminal device inwhich a control terminal is connected to a corresponding gate line, aninput terminal is connected to a corresponding data line, and an outputterminal is connected to a terminal of the liquid crystal capacitor Clcand a terminal of the storage capacitor Cst. The liquid crystalcapacitor Clc is connected between the output terminal of the switchingdevice M and a common electrode (not shown), the storage capacitor Cstmay be connected between the output terminal of the switching device Mand the common electrode or between the output terminal of the switchingdevice M and the adjacent upper gate line. The former type of thestorage capacitor Cst is called a separate wire type, and the lattertype of the storage capacitor Cst is called a previous gate type.

The gate driver 20 is connected to the plurality of the gate lines G1, .. . , Gn, and supplies a scan signal activating the switching device Mto the plurality of the gate lines G1, . . . , Gn. The data driver 30 isconnected to the plurality of the data lines D1, . . . , Dm.

Here, the switching device M may be a MOS transistor. The MOS transistormay be formed as a thin film transistor including a channel regioncomprising polycrystalline silicon. The gate driver 20 and the datadriver 30 may also include MOS transistors. These MOS transistors may beformed as thin film transistors including a channel region comprisingpolycrystalline silicon.

A thin film transistor substrate including a CMOS driving unit includingNMOS and PMOS transistors having channel regions comprisingpolycrystalline silicon will be described with reference to FIG. 2. FIG.2 is a sectional view of a driving unit of the thin film transistorsubstrate according to an embodiment of the present invention.

Referring to FIG. 2, a blocking layer 111 comprising silicon oxide orsilicon nitride is formed on a transparent insulating substrate 110.First and second semiconductor layers 150 n and 150 p are formed on theblocking layer 111. In one example, the first semiconductor layer 150 nincludes source and drain regions 153 n and 155 n, respectively, dopedwith a high-concentration n-type impurity ion, and a polycrystallinesilicon channel region 154 n undoped with impurity ion. In anotherexample, second semiconductor layer 150 p includes source and drainregions 153 p and 155 p, respectively, doped with a high-concentrationp-type impurity ion, and a polycrystalline silicon channel region 154 pundoped with impurity ion.

With respect to an NMOS transistor, low-concentration doping regions 152n doped with a low-concentration n-type impurity ion are formed betweenthe source region 153 n and the channel region 154 n and between thedrain region 155 n and the channel region 154 n.

High-concentration p-type doping regions (e.g., 112 p and 113 p) formedby ion implantation with a high-concentration p-type impurity ion arepresent in portions of the blocking layer 111 under the source region153 n and the drain region 155 n of the NMOS transistor. Peak dopingconcentrations 113 p of the high-concentration p-type doping regions inthe blocking layer 111 just under a first gate insulating layer 401 areat deeper depths than peak doping concentrations 112 p of thehigh-concentration p-type doping regions in the blocking layer 111 justunder the source region 153 n and the drain region 155 n of the NMOStransistor. A detailed description thereof will be provided later in amethod of manufacturing a thin film transistor substrate.

The first gate insulating layer 401 (for example, comprising siliconoxide) is formed on the substrate 110 having thereon the first andsecond semiconductor layers 150 n and 150 p. Second gate insulatinglayers 402 n and 402 p (for example, comprising silicon nitride) areformed on the first gate insulating layer 401.

The reason why the above-described double-layered gate insulating layerstructure is used is as follows. To reduce the threshold voltage (Vth)of a thin film transistor including a semiconductor layer made ofpolycrystalline silicon, it is necessary to form a gate insulating layerto a thin thickness. A conventional single-layered gate insulating layercomprising silicon oxide has a limitation in reduction of the thresholdvoltage of a thin film transistor due to low dielectric constant of 3.9.Furthermore, when a gate insulating layer is formed to a thin thicknessto reduce the threshold voltage of a thin film transistor, a breakdownvoltage is reduced, thereby increasing an electrostatic damage. Thus, inthis embodiment, a gate insulating layer has a double-layered structure,i.e., the first gate insulating layer 401 comprising silicon oxide andthe second gate insulating layers 402 n and 402 p comprising siliconnitride, which have about two times a higher dielectric constant thansilicon oxide, to reduce the threshold voltage of thin film transistorsand improve the performance of the thin film transistors.

The first gate insulating layer 401 covers the entire surface of thefirst and second semiconductor layers 150 n and 150 p comprisingpolycrystalline silicon. Then, first contact holes 141 n and 141 p andsecond contact holes 142 n and 142 p are formed in the first gateinsulating layer 401 to electrically connect the source regions 153 nand 153 p and the drain regions 155 n and 155 p of the first and secondsemiconductor layers 150 n and 150 p, respectively, to source electrodes173 n and 173 p and drain electrodes 175 n and 175 p, respectively, aswill be further described later.

The second gate insulating layer 402 n of the NMOS transistor is formedon the first gate insulating layer 401 to overlap with the channelregion 154 n and the low-concentration doping regions 152 n adjacent tothe channel region 154 n in the first semiconductor layer 150 n. Thesecond gate insulating layer 402 p of the PMOS transistor is formed onthe first gate insulating layer 401 to overlap with the secondsemiconductor layer 150 p. The first and second contact holes 141 p and142 p of the PMOS transistor extend from the first gate insulating layer401 to the second gate insulating layer 402 p. In one embodiment, thethickness of each of the second gate insulating layers 402 n and 402 pmust be equal to or greater than that of the first gate insulating layer401. The reason will be described later in a method of manufacturing athin film transistor substrate.

First and second gate electrodes 124 n and 124 p are respectively formedon the second gate insulating layers 402 n and 402 p of the NMOS andPMOS transistors. The first gate electrode 124 n overlaps with thechannel region 154 n of the first semiconductor layer 150 n, and thesecond gate electrode 124 p overlaps with the channel region 154 p ofthe second semiconductor layer 150 p. An inter-insulating layer 601 isformed on the resultant structure having the first and second gateelectrodes 124 n and 124 p. The first contact holes 141 n and 141 p andthe second contact holes 142 n and 142 p formed in the first gateinsulating layer 401 extend to the inter-insulating layer 601 toelectrically connect the source regions 153 n and 153 p and the drainregions 155 n and 155 p to the source electrodes 173 n and 173 p and thedrain electrodes 175 n and 175 p, respectively.

On the inter-insulating layer 601, there are formed the source electrode173 n of the NMOS transistor and the source electrode 173 p of the PMOStransistor electrically connected to the source regions 153 n and 153 pvia the first contact holes 141 n and 141 p, respectively, and the drainelectrodes 175 n and 175 p, opposite to the source electrodes 173 n and173 p with respect to the channel regions 154 n and 154 p, beingelectrically connected to the drain regions 155 n and 155 p via thesecond contact holes 142 n and 142 p, respectively. The drain electrode175 n of the NMOS transistor is connected to the source electrode 173 pof the PMOS transistor.

Now a method of manufacturing the thin film transistor substrateaccording to an embodiment of the present invention will be described ingreater detail with reference to FIGS. 3 through 12. FIG. 3 is a flowdiagram illustrating the method of manufacturing a thin film transistorsubstrate according to an embodiment of the present invention, and FIGS.4 through 12 are sequential sectional views illustrating the method ofmanufacturing the thin film transistor substrate according to anembodiment of the present invention.

Referring to FIG. 3, a first gate insulating layer, a second gateinsulating layer, and a gate conductive layer are sequentially formed ona blocking layer having thereon first and second semiconductor layers(operation S11).

In more detail, referring to FIG. 4, a blocking layer 111 is formed on atransparent insulating substrate 110. The transparent insulatingsubstrate 110 may be formed using glass, quartz, or sapphire, in oneexample, and the blocking layer 111 may be formed by deposition ofsilicon oxide (SiO₂) or silicon nitride (SiN_(x)) in another example.The blocking layer 111 serves to prevent the diffusion of impurity, etc.from the substrate 110 to first and second semiconductor layers 150 nand 150 p, and may be formed to a thickness of about 5,000 Å.

Then, amorphous silicon is formed to a thickness of, for example, about500 Å on the blocking layer 111 to form an amorphous silicon layer. Theamorphous silicon layer is crystallized by laser annealing, furnaceannealing, or solid-phase crystallization, in one example, and patternedby photolithography, to form the first and second semiconductor layers150 n and 150 p comprising polycrystalline silicon.

Then, silicon oxide and silicon nitride are sequentially deposited onthe substrate 110 having thereon the first and second semiconductorlayers 150 n and 150 p to form a first gate insulating layer 401 and asecond gate insulating layer 402. In one embodiment, the thickness ofthe second gate insulating layer 402 must be equal to or greater thanthat of the first gate insulating layer 401. For example, when thethickness of the first gate insulating layer 401 is about 350 Å, thethickness of the second gate insulating layer 402 may be about 450 Å.However, the present invention is not limited to the above-illustratedexample.

Then, a gate conductive layer 120 is formed on the second gateinsulating layer 402. The gate conductive layer 120 may be formed as asingle-layered film or a multi-layered film using aluminum, chromium,molybdenum, or an alloy thereof in one example. The gate conductivelayer 120 may have a thickness of about 3,200 Å, but the presentinvention is not limited thereto. The thickness of the gate conductivelayer 120 may be changed according to desired device characteristics.

Next, first and second photoresist film patterns are formed on theconductive layer (see operation S12 shown in FIG. 3), as shown in FIG.5.

Referring to FIG. 5, a photoresist film is formed on the gate conductivelayer 120, exposed by photolithography using a photomask 200 includinglight-shielding portions 211 and 212, light-transmission portions 221,222, and 223, and slit portions 231 and 232 for partial lighttransmission, and developed to form first and second photoresist filmpatterns 310 and 320. The first photoresist film pattern 310 is formedas a single-layered structure having a first thickness d1 on a portionof the gate conductive layer 120 corresponding to the light-shieldingportion 211 of the photomask 200. A width of the first photoresist filmpattern 310 may be changed according to a desired width of a channelregion (see 154 n shown in FIG. 2) to be formed in the firstsemiconductor layer 150 n. A portion of the second photoresist filmpattern 320 corresponding to the light-shielding portion 212 of thephotomask 200 has the first thickness d1, whereas portions of the secondphotoresist film pattern 320 corresponding to the slit portions 231 and232 of the photomask 200 have a second thickness d2. That is, the secondphotoresist film pattern 320 has a double-layered structure where anupper portion w1 has the first thickness d1 and lower portions w2 and w3have the second thickness d2. A width of the upper portion w1 of thesecond photoresist film pattern 320 depends on a desired width of achannel region (see 154 p shown in FIG. 2) to be formed in the secondsemiconductor layer 150 p, and widths of the lower portions w2 and w3depend on desired widths of source and drain regions (see 153 p and 155p shown in FIG. 2) to be formed in the second semiconductor layer 150 p.

The first and second photoresist film patterns 310 and 320 may be formedin various shapes according to desired purposes. For example, the firstand second photoresist film patterns 310 and 320 may be formed to have atrapezoidal profile shape by patterning the photoresist film in apredetermined shape, followed by heating and shrinking. In anotherexample, the first and second photoresist film patterns 310 and 320 maybe formed to have a semispherical profile shape by heating a moltenphotoresist film. The first and second photoresist film patterns 310 and320 can be used as etching masks for patterning the gate conductivelayer 120 into gate electrodes, and, at the same time, as etching masksfor forming second gate insulating layer. The first and secondphotoresist film patterns 310 and 320 can also be used as ionimplantation masks for forming the source and drain regions of the firstand second semiconductor layers 150 n and 150 p. This embodiment hasbeen illustrated that the double-layered second photoresist film pattern320 is formed using the photomask 200 including the slit portions 231and 232, but the present invention is not limited to theabove-illustrated example. The double-layered second photoresist filmpattern 320 can also be formed using a halftone mask instead of slitmask portions 231 and 232.

Next, a first gate electrode and a second gate pattern are formed(operation S13 shown in FIG. 3).

In more detail, referring to FIGS. 5 and 6, the gate conductive layer120 is patterned using the first and second photoresist film patterns310 and 320 as etching masks to form a first gate electrode 124 n and asecond gate pattern 120 p. Sidewalls of the gate conductive layer 120are over-etched by isotropic etching, e.g., wet-etching, to form thefirst gate electrode 124 n and the second gate pattern 120 p. Thesidewalls of the first gate electrode 124 n and the second gate pattern120 p may have tapered shapes to increase an adhesion with upper filmsto be formed in subsequent processes.

Next, the second gate insulating layer is patterned (operation S14 shownin FIG. 3).

In more detail, referring to FIG. 7, the second gate insulating layer402 is subjected to an etch back process using the first and secondphotoresist film patterns 310 and 320 as etching masks to form patternedsecond gate insulating layers 402 n and 402 p. The second gateinsulating layer 402 n formed beneath the first gate electrode 124 n hasa wider width than the first gate electrode 124 n. Low-concentrationdoping regions as will be described later are defined by a widthdifference between the second gate insulating layer 402 n and the firstsemiconductor layer 150 n.

Next, a source region and a drain region are formed in the firstsemiconductor layer (operation S15 shown in FIG. 3).

In more detail, referring to FIG. 8, a high-concentration n-typeimpurity ion N⁺ is injected into the first semiconductor layer 150 nusing the first gate insulating layer 401, the second gate insulatinglayers 402 n and 402 p, the first gate electrode 124 n, the second gatepattern 120 p, and the first and second photoresist film patterns 310and 320 as ion implantation masks to form a source region 153 n, a drainregion 155 n, and a channel region 154 n in the first semiconductorlayer 150 n. The channel region 154 n is a portion of the firstsemiconductor layer 150 n overlapping with the first photoresist filmpattern 310 and separates the source region 153 n and the drain region155 n and the n-type impurity ion N⁺ is not injected thereinto. Withrespect to the second semiconductor layer 150 p, the n-type impurity ionN⁺ is not injected into the second semiconductor layer 150 p due to anupper structure overlapping with the second semiconductor layer 150 p.The n-type impurity ion N⁺ may be PH₃, in one example, and an ionimplantation dose and an ion implantation energy are adjusted accordingto desired device characteristics so that a peak doping concentration isformed in the first semiconductor layer 150 n.

Next, the first and second photoresist film patterns are subjected to apartial ashing process (operation S16 shown in FIG. 3) and then a secondgate electrode is formed on the second gate insulating layer 402 p(operation S17 shown in FIG. 3).

Referring to FIGS. 8 and 9, the first and second photoresist filmpatterns 310 and 320 are subjected to an ashing process to remove thelower portions w2 and w3 having the second thickness d2 and leave onlythe upper portion w1 in the second photoresist film pattern 320,resulting in a second photoresist film pattern 320′. Then, the secondgate pattern 120 p is patterned using the second photoresist filmpattern 320′ as an etching mask to form a second gate electrode 124 p.

Next, a source region and a drain region are formed in the secondsemiconductor layer (operation S18 shown in FIG. 3).

Referring to FIG. 10, a high-concentration p-type impurity ion P⁺, e.g.,B₂H₆, is injected into the second semiconductor layer 150 p using thefirst gate insulating layer 401, the second gate insulating layers 402 nand 402 p, the first and second gate electrodes 124 n and 124 p, and thefirst and second photoresist film pattern 310 and 320′ as ionimplantation masks to form a source region 153 p, a drain region 155 p,and a channel region 154 p in the second semiconductor layer 150 p. Thechannel region 154 p is a portion of the second semiconductor layer 150p overlapping with the second photoresist film pattern 320′ andseparates the source region 153 p and the drain region 155 p and thep-type impurity ion P⁺ is not injected thereinto. To form the peakdoping concentration of the p-type impurity ion P⁺ in the secondsemiconductor layer 150 p, the p-type impurity ion P⁺ must be injectedusing a relatively high ion implantation energy since the first gateinsulating layer 401 and the second gate insulating layer 402 p areformed on the source region 153 p and the drain region 155 p of thesecond semiconductor layer 150 p. On the other hand, since only thefirst gate insulating layer 401 is formed on the source region 153 n andthe drain region 155 n of the first semiconductor layer 150 n, thep-type impurity ion P⁺ using relatively high ion implantation energy isalso injected into the blocking layer 111 under the first semiconductorlayer 150 n. In this case, as the second gate insulating layers 402 nand 402 p become thicker than the first gate insulating layer 401, i.e.,as a thickness difference between the first gate insulating layer 401and the second gate insulating layers 402 n and 402 p increases, peakdoping concentrations 112 p and 113 p of the p-type impurity ion P⁺ inthe blocking layer 111 under the first semiconductor layer 150 n are atdeeper depths. Furthermore, the peak doping concentrations 113 p in theblocking layer 111 just under the first gate insulating layer 401 are atdeeper depths relative to the peak doping concentrations 112 p of thep-type impurity ion in the blocking layer 111 just under the sourceregion 153 n and the drain region 155 n of the first semiconductor layer150 n.

Next, low-concentration doping regions are formed in the firstsemiconductor layer (operation S19 shown in FIG. 3).

Referring to FIG. 11, a low-concentration n-type impurity ion N⁻ isinjected into the first semiconductor layer 150 n using as an ionimplantation mask the resultant structure in which the first photoresistfilm pattern 310 and the second photoresist film pattern 320′ areremoved, to form low-concentration doping regions 152 n in the firstsemiconductor layer 150 n.

Next, referring to FIG. 12, the resultant structure having thelow-concentration doping regions 152 n is covered with an insulatingmaterial to form an inter-insulating layer 601. Then, theinter-insulating layer 601 is patterned by photolithography using a maskto form first contact holes 141 n and 141 p and second contact holes 142n and 142 p exposing the source regions 153 n and 153 p and the drainregions 155 n and 155 p, respectively.

Next, turning to FIG. 2, a data conductive layer (not shown) is formedon the inter-insulating layer 601 and patterned by photolithographyusing a mask to form source electrodes 173 n and 173 p and drainelectrodes 175 n and 175 p. The source electrodes 173 n and 173 p arerespectively connected to the source regions 153 n and 153 p via thefirst contact holes 141 n and 141 p, respectively, and the drainelectrodes 175 n and 175 p are connected to the drain regions 155 n and155 p via the second contact holes 142 n and 142 p, respectively. Thesource electrodes 173 n and 173 p and the drain electrodes 175 n and 175p are formed by forming a data conductive layer as a single layer madeof aluminum (Al), Al-containing metal (Al alloy), molybdenum (Mo), or Moalloy, in one example, or a multiple layer including an Al alloy layerand a chromium (Cr) or Mo alloy layer, in another example, andpatterning the data conductive layer. The data conductive layer may beformed using the same conductive material and etching method as used forthe gate conductive layer. The sidewall profiles of the sourceelectrodes 173 n and 173 p and the drain electrodes 175 n and 175 p mayhave tapered shapes to increase an adhesion with upper films insubsequent processes.

The present invention is described hereinafter with reference toflowchart illustrations of a method of manufacturing a thin filmtransistor substrate according to another embodiment of the invention.FIG. 13 is a flow diagram illustrating the method of manufacturing athin film transistor substrate according to this embodiment of thepresent invention, and FIG. 14 is a sectional view of an intermediatestructure formed in the method of manufacturing the thin film transistorsubstrate according to this embodiment of the present invention.

A method of manufacturing a thin film transistor substrate according toanother embodiment of the present invention is substantially the same asthat of the previous embodiment except that the forming of a sourceregion and a drain region in a first semiconductor layer is performedimmediately before forming a source region and a drain region in asecond semiconductor layer. Thus, the features of this embodiment thatdiffer from the previous embodiment will be described hereinafter withreference to FIGS. 4-7 and 9-14.

First, as shown in FIG. 4, first and second gate insulating layers 401and 402 and a gate conductive layer 120 are sequentially formed on ablocking layer 111 having thereon first and second semiconductor layers150 n and 150 p (see operation S21 shown in FIG. 13).

Next, as shown in FIG. 5, a first photoresist film pattern 310 is formedto a first thickness d1 on a portion of the gate conductive layer 120overlapping with the first semiconductor layer 150 n, and a secondphotoresist film pattern 320 is formed in a double-layered structureincluding an upper portion w1 with the first thickness d1 and lowerportions w2 and w3 with a second thickness d2 thinner than the firstthickness d1 on a portion of the gate conductive layer 120 overlappingwith the second semiconductor layer 150 p (see operation S22 shown inFIG. 13).

Next, as shown in FIG. 6, the gate conductive layer 120 is isotropicallyetched using the first and second photoresist film patterns 310 and 320as etching masks to form a first gate electrode 124 n and a second gatepattern 120 p (see operation S23 shown in FIG. 13).

Next, as shown in FIG. 7, the second gate insulating layer 402 ispatterned by an etch back process using the first and second photoresistfilm patterns 310 and 320 as etching masks to form patterned second gateinsulating layers 402 n and 402 p (see operation S24 shown in FIG. 13).

Next, as shown in FIGS. 7 and 9, the first and second photoresist filmpatterns 310 and 320 are subjected to an ashing process to remove thelower portions w2 and w3 from the second photoresist film pattern 320,resulting in a second photoresist film pattern 320′ (see operation S25shown in FIG. 13).

Then, the second gate pattern 120 p is patterned using the secondphotoresist film pattern 320′ as an etching mask to form a second gateelectrode 124 p (see operation S26 shown in FIG. 13).

Next, as shown in FIG. 14, a source region 153 n and a drain region 155n are formed in the first semiconductor layer 150 n (see operation S27shown in FIG. 13).

In more detail, a high-concentration n-type impurity ion N⁺ is injectedinto the first semiconductor layer 150 n using as ion implantation masksthe first gate insulating layer 401, the second gate insulating layers402 n and 402 p, the first and second gate electrodes 124 n and 124 p,and the first and second photoresist film patterns 310 and 320′, to formthe source region 153 n, the drain region 155 n, and a channel region154 n in the first semiconductor layer 150 n. The n-type impurity ion N⁺may be PH₃ in one example. An ion implantation dose and an ionimplantation energy are adjusted according to device characteristics sothat a peak doping concentration can be formed in the firstsemiconductor layer 150 n. Thus, the n-type impurity ion N⁺ is notinjected into the second semiconductor layer 150 p covered with thesecond gate insulating layer 402 p and the first gate insulating layer401.

Next, as shown in FIG. 10, a high-concentration p-type impurity ion P⁺,e.g., B₂H₆, is injected into the second semiconductor layer 150 p usingas an ion implantation mask the resultant structure in which the sourceregion 153 n and the drain region 155 p are formed in the firstsemiconductor layer 150 n, to form a source region 153 p, a drain region155 p, and a channel region 154 p in the second semiconductor layer 150p (see operation S28 shown in FIG. 13).

Next, as shown in FIG. 11, the first and second photoresist filmpatterns 310 and 320′ are removed, and a low-concentration n-typeimpurity ion N⁻, e.g., PH₃, is injected into the first semiconductorlayer 150 n using as an ion implantation mask the resultant structurewherein the first and second photoresist film patterns 310 and 320′ areremoved, to form low-concentration doping regions 152 n (see operationS29 shown in FIG. 13).

Next, as shown in FIG. 12, the resultant structure having thelow-concentration doping regions 152 n is covered with an insulatingmaterial to form an inter-insulating layer 601. The inter-insulatinglayer 601 is patterned to form first contact holes 141 n and 141 p andsecond contact holes 142 n and 142 p exposing the source regions 153 nand 153 p and the drain regions 155 n and 155 p, respectively.

Next, as shown in FIG. 2, source electrodes 173 n and 173 p connected tothe source regions 153 n and 153 p via the first contact holes 141 n and141 p, respectively, and drain electrodes 175 n and 175 p connected tothe drain regions 155 n and 155 p via the second contact holes 142 n and142 p, respectively, are formed on the inter-insulating layer 601.

While the above-described embodiments have illustrated that the sourceand drain regions of a second semiconductor layer are formed afterforming the source and drain regions of a first semiconductor layer, thepresent invention is not limited thereto. It should be understood thatthe source and drain regions of a second semiconductor layer can beformed prior to forming the source and drain regions of a firstsemiconductor layer.

Advantageously, according to the method of manufacturing a thin filmtransistor substrate of the present invention, since the formation offirst and second gate insulating layers and first and second gateelectrodes on a substrate having thereon first and second semiconductorlayers and the formation of impurity ion implantation regions in thefirst and second semiconductor layers are achieved using only a singlemask, process efficiency is increased, resulting in an increase in theyield and a reduction of manufacturing costs. In concluding the detaileddescription, those skilled in the art will appreciate that manyvariations and modifications can be made to the above-describedembodiments without substantially departing from the principles of thepresent invention as set forth in the appended claims. Therefore, thedisclosed embodiments of the invention are used in a generic anddescriptive sense only and not for purposes of limitation.

1. A thin film transistor substrate, comprising: a first conductive typeMOS transistor including: a first semiconductor layer formed on ablocking layer and having first conductive type low-concentration dopingregions adjacent to both sides of a channel region, first conductivetype source/drain regions adjacent to the first conductive typelow-concentration doping regions, a first gate insulating layer formedon the first semiconductor layer, a first portion of a second gateinsulating layer formed on the first gate insulating layer andoverlapping only with the channel region and the low-concentrationdoping regions of the first semiconductor layer, and a first gateelectrode formed on the second gate insulating layer; and a secondconductive type MOS transistor including: a second semiconductor layerformed on the blocking layer and having second conductive typesource/drain regions adjacent to both sides of a channel region, thefirst gate insulating layer formed on the second semiconductor layer, asecond portion of the second gate insulating layer formed on the firstgate insulating layer and overlapping with the second conductive typesource/drain regions of the second semiconductor layer, and a secondgate electrode formed on the second gate insulating layer.
 2. The thinfilm transistor substrate of claim 1, wherein the thickness of thesecond gate insulating layer is equal to or greater than the thicknessof the first gate insulating layer.
 3. The thin film transistorsubstrate of claim 1, further comprising a second conductive type dopingimpurity under the first conductive type source/drain regions in thefirst semiconductor layer of the first conductive type MOS transistor.4. The thin film transistor substrate of claim 1, wherein the firstconductive type is n-type and the second conductive type is p-type. 5.The thin film transistor substrate of claim 1, wherein the first gateinsulating layer comprises a silicon oxide film.
 6. The thin filmtransistor substrate of claim 1, wherein the second gate insulatinglayer comprises a silicon nitride film.
 7. The thin film transistorsubstrate of claim 1, wherein the second portion of the second gateinsulating layer overlaps only with the second conductive typesource/drain regions and channel region of the second semiconductorlayer.
 8. The thin film transistor substrate of claim 1, furthercomprising: an inter-insulating layer formed on the first gateinsulating layer, the second gate insulating layer, the first gateelectrode and the second gate electrode; a first contact hole in theinter-insulating layer exposing a portion of the first conductive typedrain region; a second contact hole in the inter-insulating layerexposing a portion of the second conductive type source region; and anelectrode layer formed on the inter-insulating layer, an exposed portionof the first conductive type drain region and an exposed portion of thesecond conductive type source region.